1. Field of the Invention
This invention relates to processor timing circuits. More specifically, this invention relates to a circuit and operating method for generating processor wait states.
2. Description of the Relevant Art
Functional testing of complex circuits, such as microprocessor circuits, involves the measurement of many various operating parameters. Many of these measurements are difficult to perform without special purpose test circuits and procedures.
In one example of such a functional test, the performance of a processor may be tested by measuring the execution time of a particular standard benchmark software routine. These measurements are useful for improving or optimizing processor performance under various operating conditions. One important operating condition of a processor relates to the processor's latency of operation. A wait state is a designation of the latency of a processor, the time interval between the instant at which a call for data is initiated and the instant the actual transfer of the data begins.
One valuable assessment of processor performance is measure of the time taken by a particular standard benchmark software routine to execute as a function of the latency, the number of wait states, of the processor. More specifically, a valuable measure of processor performance involves an analysis of the execution time of the processor as the processor executes a particular type of data access or input/output cycle, such as a read cycle, a write cycle, a read-write cycle or a burst access cycle, for example. Typically, the cycle types tested would encompass every type of data movement and every type of bus activity that is performed by a processor bus.
For some cycle types, variation in the number of wait states only has a marginal effect on the execution time of the processor. For other cycle types, varying the number of wait states greatly influences the execution time of software on the processor.
What is desired is a test apparatus and testing method that facilitate and provide for analysis of processor performance as a function of processor latency. More particularly, what is desired is a test apparatus and testing method that assist an analysis of processor performance when executing a particular type of data access or input/output cycle as a function of processor wait states.